1. Field of the Invention
The present invention is directed generally to electronic design automation (EDA) tools used, for example, in the design of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a method and computer program for automatically configuring data representative of an integrated circuit design to generate different scenarios for performing static timing analysis on different portions of the integrated circuit design that may be much smaller than the overall design.
2. Description of Related Art
One measure of the performance of an integrated circuit is the maximum allowable clock frequency. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing that determines the maximum allowable clock frequency. Static timing analysis is a method of computing the expected timing of a digital circuit without requiring a full circuit simulation using simplified delay models. As a result of the simplification, the capability to estimate the effects of logical interactions between signals is limited. Nevertheless, static timing analysis has become a mainstay of integrated circuit design over the last few decades.